1. Field of the Invention
The present invention relates to a data transfer apparatus and a data transfer system intended to transfer data continuously input or output to/from a main memory without any omission. In particular, the present invention relates to a data transfer apparatus and a data transfer system that transfer continuous data on a general-purpose bus such as a PCI bus. The present invention also relates to a recording medium storing a program that commands a computer to execute all or some of functions of each component of the data transfer apparatus or data transfer system.
2. Description of the Prior Art
As a conventional system that transfers data input/output to/from external devices with a main memory connected to a system bus, a PCI bus used by a personal computer is known (OPEN DESIGN No. 7 xe2x80x9cDetails of PCI Bus and Steps for its Applicationsxe2x80x9d CQ Publishing Co., Ltd.).
FIG. 15 shows a system block diagram of the PCI bus and with reference now to the attached drawings a data transfer example of the PCI bus will be explained below.
In FIG. 15, 101 is a central processing unit (hereinafter referred to as xe2x80x9cCPUxe2x80x9d), 102 is a main memory and 103 is a memory controller that controls the main memory 102, and these are connected by a host bus 104. 105 is a host PCI bridge, 106 is an I/O device, 107 is a PCI board having a device that allows data input/output to/from external devices, 109 is an extended bus bridge and 108 is a PCI bus that connects these. 110 is a PCI bus controller that controls the PCI bus, 111 is a buffer memory that stores input data temporarily and 112 is a buffer controller.
When data is input from the input terminal of a PCI board 107, the data is temporarily stored in a buffer memory 111. The amount of data stored in the buffer memory 111 is controlled by a buffer controller 112 and if a predetermined amount of data is reached, a transfer request is issued to the PCI bus controller 110. After receiving the transfer request from the buffer controller 112, the PCI bus controller 110 issues a bus access request signal onto the PCI bus 108. The bus access request signal is transmitted to the host PCI bridge 105 and enables the PCI board 107 to access the PCI bus 108 if there is no access request from other PCI boards. Given the access right, the PCI bus controller 110 issues a transfer enable to the buffer controller 112 and immediately starts a data transfer from the buffer memory 111. The data transferred from the PCI board 107 is temporarily stored in the host PCI bridge 105 and stored in the main memory 102 through the host bus 104 and the memory controller 103.
As shown above, the conventional example above with the buffer memory 111 can temporarily store data input from external devices until the right of access to the PCI bus 108 is given and transfer all data to the main memory 102 without any omission. The data stored in the main memory 102 is transformed to various formats by the CPU 101.
In a personal computer, an add-on card and mother board are connected by a communication path, which is a so-called computer bus such as PCI interface, and the electrical characteristics and the signal format of a computer bus are often made open to general public, which originates great problems such as illegal copies of digital information transmitted through the above computer bus and subsequent data alteration.
However, performing a continuous input/output data transfer between external devices and the main memory on the conventional PCI bus involves the following problems:
First, various kinds of PCI boards are connected to the PCI bus 108, each PCI board issues a request for access to the PCI bus 108 at irregular time intervals and transfers data of undefined lengths, which makes irregular intervals at which access to the PCI bus 108 is permitted. If it occurs frequently that the access enable issuance time interval exceeds the value obtained by dividing the capacity of the buffer memory 111 by the transfer rate of continuously input/output data, then the continuously input/output data will overwrite (when input to the main memory 102) on the buffer memory 111, resulting in data omissions or the buffer memory 111 becoming empty (when output from main memory 102) leading to an empty transfer.
Moreover, since the PCI bus 108 is a general-purpose bus, if data input is video/voice data, the PCI bus 108 easily allows other PCI boards or I/O devices to incorporate the input data, which causes another problem of easily allowing illegal copies.
The present invention has taken into account the problems above of the conventional PCI bus transfer system and it is an objective of the present invention to provide a data transfer apparatus and data transfer system capable of preventing continuously input/output data from being interrupted even if bus access enable issuance time intervals become irregular.
The 1st invention of the present invention is a data transfer apparatus temporarily storing continuously input data and transmitting the input data to a transfer destination according to an input enable signal issued by said transfer destination through a first bus, comprising:
an input buffer memory that temporarily stores said continuously input data;
a transfer controller, connected with said transfer destination through said first bus, that acquires said input enable signal through said first bus and transmits said temporarily stored input data output from said input buffer memory to said transfer destination through said first bus;
a second bus that performs data transfer between said input buffer memory and said transfer controller; and
a buffer controller that controls the output of said input buffer memory according to said input enable signal,
wherein said input buffer memory capacity CAPW satisfies the following Mathematical formula 1, where the input rate of said continuously input data is T1 and the maximum assumed value of the transmission time interval of said input enable signal issued by said transfer destination is TW:                     CAPW        ≧                  TW          xc3x97          T1                                    [                  Mathematical          ⁢                      xe2x80x83                    ⁢          formula          ⁢                      xe2x80x83                    ⁢          1                ]            
The 2nd invention of the present invention is a data transfer apparatus temporarily storing output data transmitted from a transfer destination through a first bus according to an output enable signal issued by said transfer destination and continuously outputs the data, comprising:
a transfer controller connected with said transfer destination through said first bus that acquires said output enable signal and said transmitted output data through said first bus;
an output buffer memory that temporarily stores and continuously outputs said transmitted output data;
a second bus that performs data transfer between said output buffer memory and said transfer controller; and
a buffer controller that controls the input to said output buffer memory according to said output enable signal,
wherein said output buffer memory capacity CAPR satisfies the following Mathematical formula 2, where the output rate of said continuously output data is T2 and the maximum assumed value of the transmission time interval of said output enable signal issued by said transfer destination is TR:                     CAPR        ≧                  TR          xc3x97          T2                                    [                  Mathematical          ⁢                      xe2x80x83                    ⁢          formula          ⁢                      xe2x80x83                    ⁢          2                ]            
The 3rd invention of the present invention is a data transfer apparatus temporarily storing continuously input data, transmitting the input data to a transfer destination through a first bus according to an input enable signal issued by said transfer destination and temporarily storing output data transmitted from said transfer destination through the first bus according to an output enable signal issued by said transfer destination and continuously outputs the output data, comprising:
an input buffer memory that temporarily stores said continuously input data;
an output buffer memory that temporarily stores and continuously outputs said transmitted output data;
a transfer controller, connected with said transfer destination through said first bus, that acquires said input enable signal, said output enable signal and said transmitted output data through said first bus, transmits said temporarily stored input data output from said input buffer memory to said transfer destination through said first bus and transmits said output data to said output buffer memory through said first bus;
a second bus that performs data transfer between said input buffer memory, said output buffer memory and said transfer controller; and
a buffer controller that controls the output of said input buffer memory according to said input enable signal and controls the input to said output buffer memory according to said output enable signal,
wherein said input buffer memory capacity CAPW satisfies the following Mathematical formula 1, where the,input rate of said continuously input data is T1 and the maximum assumed value of the transmission time interval of said input enable signal issued by said transfer destination is TW; and
said output buffer memory capacity CAPR satisfies the following Mathematical formula 2, where the output rate of said continuously output data is T2 and the maximum assumed value of the transmission time interval of said output enable signal issued by said transfer destination is TR:                     CAPW        ≧                  TW          xc3x97          T1                                    [                  Mathematical          ⁢                      xe2x80x83                    ⁢          formula          ⁢                      xe2x80x83                    ⁢          1                ]                                CAPR        ≧                  TR          xc3x97          T2                                    [                  Mathematical          ⁢                      xe2x80x83                    ⁢          formula          ⁢                      xe2x80x83                    ⁢          2                ]            
The 4th invention of the present invention is the data transfer apparatus according to said the 1st or 3rd inventions, further comprising transfer control means on the apparatus side that detects whether said input data contains a predetermined protection signal, extracts the protection signal and enables transmission to said transfer destination according to the presence/absence of said protection signal or said protection signal.
The 5th invention of the present invention is the data transfer apparatus according to any one of said the 1st, 3rd and 4th inventions, further comprising encryption,means that detects whether said input data contains a predetermined protection signal and if said input data contains said predetermined protection signal, encrypts said input data and transmits the encrypted input data to said transfer destination.
The 6th invention of the present invention is the data transfer apparatus according to said the 4th or 5th inventions, further comprising authentication means that, if authentication of said data transfer destination is considered necessary, said authentication is performed.
The 7th invention of the present invention is the data transfer apparatus according to said the 4th, 5th or 6th inventions, comprising said transfer controller that transmits not only,data obtained by encrypting said input data, but also encryption mode information without encryption set according to said protection signal.
The 8th invention of present invention is the data transfer apparatus according to said the 5th, 6th or 7th inventions, further comprising encryption means in which said input data is multiplexed data obtained by multiplexing a plurality of programs in a packet, selectively encrypted for every said programs and transmitted to said transfer destination.
The 9th invention of the present invention is the data transfer apparatus according to said the 8th invention comprising said transfer controller that transmits packet identifiers to identify said plurality of programs without encryption to said transfer destination.
The 10th invention of the present invention is the data transfer apparatus according to said the 8th or 9th inventions, comprising said transfer controller that transmits data with said encryption mode information for every said programs of said multiplexed packet data.
The 11th invention of the present invention is a data transfer system comprising:
a data transfer apparatus according to one of said the 1st to 10th inventions;
a main memory and a central processing unit that controls the main memory comprising said transfer destination; and
a transfer bus, which is said first bus.
The 12th invention of the present invention is the data transfer system according to said the 11th invention, wherein said central processing unit sets the transfer size corresponding to said input enable signal in such a way that said input buffer memory becomes empty when a transfer is completed and/or sets the transfer size corresponding to said output enable signal in such a way that said output buffer memory is left without empty space when the transfer is completed.
The 13th invention of the present invention is the data transfer system according to said the 11th or 12th inventions, wherein said data transfer apparatus is the data transfer apparatus according to said the 3rd invention and comprises transfer control-means that switches between said input data transfer and said output data transfer by means of time division according to a relationship between said input buffer memory capacity, said input rate, capacity of said output buffer memory and said output rate, and said input enable signal and said output enable signal are issued according to switching performed by said transfer control means.
The 14th invention of the present invention is the data transfer system according to said the 11th, 12th or 13th inventions, wherein said data transfer apparatus is the data transfer apparatus according to said the 2nd or 3rd inventions, and
if said output data is obtained by separating video/voice multiplexed data into a continuous video data group, which is a group of continuous video data and a continuous voice data group, which is a group of continuous voice data,
said continuous video data group and said continuous voice data group, which are mutually corresponding to each other, are transmitted in response to said two output enable signals issued one after the other, respectively,
the transfer timings of said two output enable signals are determined by the transfer control means in such a way that said continuous video data group and said continuous voice data group, which are mutually corresponding to each other, are output from said output buffer memory continuously.
The 15th invention of the present invention is the data transfer system according to any one of said the 11th to 14th inventions, wherein said data transfer apparatus is the data transfer apparatus according to said the 2nd or 3rd and comprises transfer control means on the transfer destination side that detects whether said output data contains a predetermined protection signal and enables transmission to said data transfer apparatus according to said protection signal.
The 16th invention of the present invention is the data transfer system according to said the 11th, 12th , 13th or 14th inventions, wherein said data transfer apparatus is the data transfer apparatus according to said the 2nd or 3rd inventions, comprising transfer control means on the transfer destination side that, if said output data is encrypted, detects whether said output data contains predetermined encryption mode information or not, carries out authentication on said data transfer apparatus according to said encryption mode information and enables transmission to said data transfer apparatus only when said data transfer apparatus is authenticated.
The 17th invention of the present invention is the data transfer apparatus according to said the 2nd inventions, further comprising, authentication means that if said output data is encrypted and contains predetermined encryption mode information carries out necessary authentication on said transfer destination according to said predetermined encryption mode information and decryption means that decrypts said encrypted output data.
The 18th invention of the present invention,is the data transfer apparatus according to said the 17th invention, comprising, authentication means that if said output data contains multiplexed data made up of a plurality of programs multiplexed into packets and then encrypted and predetermined encryption mode information carries out necessary authentication on said transfer destination according to said predetermined encryption mode information and decryption means that selectively decrypts said encrypted output data for every said program.
The 19th invention of the present invention is a program recording medium storing a program that commands a computer to execute all or some of functions demonstrated by each means or each component of the data transfer apparatus or data transfer system according to one of said the 1st to 18th inventions.